Identifying And Improving Robust Designs Using Statistical Timing Anaysis

ABSTRACT

Statistical timing analysis techniques can be used to lead to the construction of robust circuits in a consistent manner through the entire design flow of synthesis, placement and routing. An exemplary technique can include receiving library data for a design including timing models. By comparing implementations of this data, a robust circuit can be defined based on a set of criteria, which can include worst negative slack, endpoint slack distribution, timing constraint violations, and total negative slack. At this point, statistical timing analysis can be used to drive logic changes that generate improved robustness in the design. The statistical timing analysis can use a static timing delay associated with the arc in statistical timing analysis as a mean and a specified percentage of the mean as the standard deviation.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to integrated circuit (IC) designs and inparticular to identifying robust designs and improving such design usingstatistical timing analysis.

2. Related Art

FIG. 1 illustrates a simplified representation of an exemplary digitalIC design flow. At a high level, the process starts with the productidea (step 100) and is realized in an EDA software design process (step110). When the design is finalized, it can be taped-out (event 140).After tape out, the fabrication process (step 150) and packaging andassembly processes (step 160) occur resulting, ultimately, in finishedchips (result 170).

The EDA software design process (step 110) is actually composed of anumber of steps 112-130, shown in linear fashion for simplicity. In anactual ASIC design process, the particular design might have to go backthrough steps until certain tests are passed. Similarly, in any actualdesign process, these steps may occur in different orders andcombinations. This description is therefore provided by way of contextand general explanation rather than as a specific, or recommended,design flow for a particular ASIC.

A brief description of the components steps of the EDA software designprocess (step 110) will now be provided:

System design (step 112): The designers describe the functionality thatthey want to implement, they can perform what-if planning to refinefunctionality, check costs, etc. Hardware-software architecturepartitioning can occur at this stage. Exemplary EDA software productsfrom Synopsys, Inc. that can be used at this step include ModelArchitect, Saber, System Studio, and DesignWare® products.

Logic design and functional verification (step 114): At this stage, theVHDL or Verilog code for modules in the system is written and the designis checked for functional accuracy. More specifically, the design ischecked to ensure that it produces the correct outputs. Exemplary EDAsoftware products from Synopsys, Inc. that can be used at this stepinclude VCS, VERA, DesignWare®, Magellan, Formality, ESP and LEDAproducts.

Synthesis and design for test (step 116): Here, the VHDL/Verilog istranslated to a netlist. The netlist can be optimized for the targettechnology. Additionally, the design and implementation of tests topermit checking of the finished chip occurs. Exemplary EDA softwareproducts from Synopsys, Inc. that can be used at this step includeDesign Compiler®, Physical Compiler, Test Compiler, Power Compiler, FPGACompiler, Tetramax, and DesignWare® products.

Netlist verification (step 118): At this step, the netlist is checkedfor compliance with timing constraints and for correspondence with theVHDL/Verilog source code. Exemplary EDA software products from Synopsys,Inc. that can be used at this step include Formality, PrimeTime, and VCSproducts.

Design planning (step 120): Here, an overall floorplan for the chip isconstructed and analyzed for timing and top-level routing. Exemplary EDAsoftware products from Synopsys, Inc. that can be used at this stepinclude Astro and IC Compiler products.

Physical implementation (step 122): The placement (positioning ofcircuit elements) and routing (connection of the same) occurs at thisstep. Exemplary EDA software products from Synopsys, Inc. that can beused at this step include the Astro and IC Compiler products.

Analysis and extraction (step 124): At this step, the circuit functionis verified at the physical and electrical levels. Exemplary EDAsoftware products from Synopsys, Inc. that can be used at this stepinclude AstroRail, PrimeRail, Primetime, and Star RC/XT products.

Physical verification (step 126): At this step various checkingfunctions are performed to ensure correctness for: manufacturing,electrical issues, lithographic issues, and circuitry. Exemplary EDAsoftware products from Synopsys, Inc. that can be used at this stepinclude the Hercules product.

Resolution enhancement (step 128): This step involves geometricmanipulations of the layout to improve manufacturability of the design.Exemplary EDA software products from Synopsys, Inc. that can be used atthis step include Proteus, ProteusAF, and PSMGen products.

Mask data preparation (step 130): This step provides the “tape-out” datafor production of masks for lithographic use to produce finished chips.Exemplary EDA software products from Synopsys, Inc. that can be used atthis step include the CATS(R) family of products.

Netlist verification (step 118) can provide the expected timing of adigital circuit without simulation. This netlist verification technique,called static timing analysis (STA), provides a detailed analysis of thetiming behavior of the circuit independent of the combinations of inputvalues.

In STA terminology, a timing constraint is a budget of time that isavailable for circuit signals to propagate and be satisfactorily read atan output or captured by a memory element. The timing constraints arecaptured by user-specified information such as the clocking scheme,output loads, etc. A “critical path” is defined as the path between aninput pin or an output of a memory element and an output pin or an inputof a memory element which violates a timing constraint. The pin at whichthe timing check is performed is called an endpoint. Timing constraintscan be categorized into two forms. A set-up constraint is one thatrequires the signal to be stable no later than the budget. A holdconstraint is one that requires the signal to change no earlier than thebudget. For sake of exposition and without loss of generality, only thefirst form is referred to herein. The arrival time of a pin is definedas time that the signal at the pin stabilizes. In static timing, thearrival can be computed using the “add” and “maximum” operations. Therequired time of a pin is the time at which the signal must stabilize tomeet a timing constraint. In static timing, the required time can becomputed using the “subtract” and “minimum” operations. The “slack” of apin can be defined as the difference between the required time and thearrival time. Thus, a positive slack means that the overall delay of thecircuit is acceptable (and, if desirable, arrival time at that pin caneven be increased), whereas a negative slack means that the path is tooslow and therefore must be sped up to avoid adversely affecting theoverall delay of the circuit.

Over the last few years, variations in delay have concerned many in theindustry. Delay variations can arise from changes in the operatingconditions such as voltage and temperature as well as process variationsthat arise during manufacturing. However, in the context of a designflow, variations in delay can also stem from the optimization indown-stream tools, the refinement of models used in computation as thedesign evolves, and any changes to the design (i.e. specificationchanges).

Unfortunately, characterizing each cause of the change and thenattempting to define the “robustness” of a circuit with respect to thatchange would require significant resource allocation. Therefore, therearises a need for a method and an apparatus to construct change-tolerantdesigns in a cost-effective manner.

A relatively new extension to static timing analysis known asstatistical timing analysis has been introduced. This technology hasbeen designed to model variations in circuit delays caused by processvariations. Delays are represented by statistical distributions and theanalysis step propagates distributions for arrival (required) times byapplying the “add” and “maximum” (“subtract” and “minimum”) operationsto these distributions. This approach requires significant resourceallocation to characterizing the delay behavior for each process change.

SUMMARY OF THE INVENTION

In accordance with one aspect of the invention, statistical timinganalysis techniques are used for the construction of robust circuits ina consistent manner through the entire design flow of synthesis,placement and routing. An exemplary technique can include receivinglibrary data for a design including timing models. By comparingimplementations of this data, the tolerance of a circuit to delayvariations can be characterized using several criteria. Typical criteriacan include worst negative slack, endpoint slack distribution, number oftiming constraint violations, and total negative slack. These criteriaare defined using well known concepts in static timing analysis. At thispoint, statistical timing analysis can be used to drive logic changesthat generate improved robustness in the design.

Notably, statistical timing analysis models a statistical delaydistribution on an arc (i.e. a path between pins) of the design instatic timing analysis (STA). The need for characterization delaychanges to each source of variation can be advantageously circumventedby using the delay associated with an arc in static timing analysis as amean and a user-specified percentage of the mean as the standarddeviation. Thus, in this method statistical timing analysis attributesthe variation to the gates without seeking to identify the cause, whileusing the typical behavior for gate delays. As a result, each path canbe appropriately constrained. For example, longer paths have largervariation with bigger opportunity for statistical cancellation to appearon the mean delay.

In one embodiment, performing the statistical timing analysis canfurther include determining a slack distribution at endpoints of thedesign for use as a cost metric in design optimization. For example, thecost metric can include computing a probability of an endpoint failingto meet timing constraints. The probability can be computed fromstatistical timing analysis (which provides a probability densityfunction for the arrival time at an end-point). Notably, thisprobability can also be used to improve the robustness of the design.

As described in further detail below, statistical timing analysistechnology developed in the context of handling process variations canbe advantageously used to guide the optimization for robust circuits.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 illustrates a simplified representation of an exemplary digitalASIC design flow.

FIG. 2 illustrates an endpoint slack distribution graph plotting twoimplementations of the same design/circuit after static timing analysisin the synthesis step.

FIG. 3A illustrates an inverter chain which includes a plurality ofinverters, wherein each inverter has a gate delay represented bypossibly different normal distribution curves.

FIG. 3B illustrates a normal distribution for a gate that includesapproximately 100% of possible values for the delay within 3 standarddeviations from the mean.

FIG. 3C illustrates an exemplary gate that has delays associated withinput paths and internal paths (both referenced generically as arcs).

FIG. 3D illustrates how variation can be reduced by making a gatefaster.

FIG. 4 illustrates an exemplary statistical timing analysis techniquefor generating circuits in a design flow for an implementation process.

DETAILED DESCRIPTION OF THE FIGURES

Various steps of an integrated circuit (IC) design flow (e.g. synthesis,placement, clock tree analysis, and routing) use delays of gates andnets for optimization. However, these delays may vary significantlybetween steps. For example, in the absence of feedback, optimizingdownstream tools can result in different delay computations. Moreover,models for later stages in the IC design flow are typically moreaccurate because more information is then available. Other delayvariations may be due to changing the specification (e.g. a usertargeting 550 MHz versus 500 MHz), technology (i.e. the process used infabrication), or operating conditions (i.e. the environment including,but not limited to, temperature, rail power supply, etc.).Characterizing each cause of a delay change and defining robustness withrespect to the change is a complex task that inhibits itscommercialization.

Notably, as described hereafter, the definition of a “robust” circuitcan be general enough to apply to each step of the IC design flow whileallowing the construction of change-tolerant designs in a cost-effectivemanner. Thus, a robust circuit in the synthesis step will probably alsobe a robust circuit in the placement step (or at the least minimizeproblems in the placement step). Note also that the concept ofrobustness is comparative rather than absolute. Thus, robustness, asdescribed herein, is based on comparing a plurality of circuits.Advantageously, robustness can be generically defined using the STAconcept of negative slack.

A robust circuit can be defined as meeting certain criteria. Forexample, using one simple definition, a circuit C is more robust thancircuit D if the following three criteria are met. First, circuit C hasidentical or better worst negative slack than circuit D. Second, circuitC has identical or better total negative slack than circuit D. Third,circuit C has much fewer endpoints in the design that violate timingconstraints than circuit D (wherein an endpoint is any point where ifthere is a violation, then the circuit fails).

Another definition for a robust circuit using endpoint slackdistribution can also be developed. In one embodiment, the endpoints(sorted with increasing slack) can be plotted with the endpoint numberas the x-value and the slack as the y-value. The resulting curve iscalled an endpoint slack distribution curve. In one embodiment, circuitC is more robust than circuit D if its endpoint slack distribution curvelies entirely above the endpoint slack distribution curve for circuit D.If limited sections of one curve extend above the other curve, then itmay be beneficial to determine the circuit whose left most portion ofthe curve (most critical) is above to be more robust.

For example, FIG. 2 illustrates an endpoint slack distribution graph 200plotting two implementations of the same design/circuit after statictiming analysis in the synthesis step. These implementations are shownby curves 201 and 202. Designs can have any number of endpoints, e.g. upto tens or even hundreds of thousands of endpoints. The two circuitimplementations in FIG. 2 each have approximately 16,000 endpoints thatare sorted from worst negative slack to best positive slack.

In graph 200, because curve 201 lies entirely above curve 202, thecircuit represented by curve 201 is more robust than the circuitimplementation represented by curve 202. In other words, given the twocircuits subjected to variations, the circuit represented by curve 201is less likely to incur failures than the circuit associated with curve202. Specifically, note that the circuit represented by curve 201 hassignificantly fewer violating endpoints as shown by an endpoint range203 (which starts at the point where curve 201 crosses the zero slackaxis and ends where curve 202 crosses the zero slack axis). Moreover,the circuit represented by curve 201 has better total negative slackthan the circuit represented by curve 201. Note that the total negativeslack of a circuit is the area between the portion of the curve belowthe x-axis and the x-axis. The measure of improvement in total negativeslack associated with curve 201 is indicated in graph 200 by an area 204(which is defined by the area above curve 202, below the zero slackaxis, and not including the total negative slack associated with thecircuit represented by curve 201). Note that all metrics above are welldefined in the context of static timing analysis.

In accordance with analyzing a logic gate (hereinafter gate) usingstatistical timing, the gate delay is recognized to have a mean and astandard deviation (as opposed to static timing that would have a fixednumber to represent gate delay). For example, referring to FIG. 3A, aninverter chain 300 includes 10 inverters 301-310, each inverter having agate delay represented by a normal distribution 320. Note that inverters301-310 can have different values of means and standard deviations(thus, normal distribution 320 is merely meant to represent a genericnormal distribution). In the normal distribution 320 and referring toFIG. 3B, the mean (u) occurs at the mid-point of the gate delay values(x-axis). Approximately 68% of the values are within one standarddeviation (σ) from the mean, approximately 95% of the values are withintwo standard deviations (2σ) from the mean, and approximately 100% arewithin three standard deviations (3σ) from the mean. Because the y-axisin a normal distribution represents probability, the probability of thegate having a delay less than or greater than a particular value can befound by determining the area under the curve of normal distribution 320using that particular value to define an edge. Thus, each inverter has aprobability density function (PDF). Statistical timing analysis providesthe basis to compute the PDF for the arrival time of any pin (such asthe output of inverter 310) from the gate delay PDFs. The PDF for thearrival time of a pin can be used to compute the probability of the pinfailing to meet timing.

The key observation to using statistical timing analysis to constructrobust circuits is that statistical timing analysis can expose criticalpaths in the circuit which are normally hidden by static timinganalysis. Specifically, consider the case where multiple critical pathsconverge at the output pin of a gate (e.g. an AND gate, an OR gate,etc.). In this case, each path has the same mean delay and standarddeviation values. When a statistical maximum computation is carried outfor the output pin, the resultant mean of statistical maximum is greaterthan the individual mean of each of the paths. The larger the number ofpaths, the greater the push out of the statistical mean. Thiscomputation can be characterized as “exposing” the number of criticalpaths. For example, the statistical maximum of two arrival distributionsthat are identical and normal with mean 5.0 and standard deviation 0.1is approximated by a normal distribution with mean 5.05 and standarddeviation 0.08. In contrast, a static analysis to determine a maximumdelay value is unable to differentiate between cases with differentnumber of critical paths. For example the static maximum of one or morearrival values of 5.0 is still 5.0. Thus, in a statistical timinganalysis, a pin with multiple critical paths has a larger arrival timemean (compared to a static mean). As a result, statistical timinganalysis advantageously obviates the need for concepts such as criticalrange and tie counts (which are used in circuit optimization usingstatic timing analysis). A similar behavior is seen when the statisticalminimum is computed for the required time computation for criticaldistributions. In this case, the resultant mean of the statisticalminimum is smaller than the individual mean of each.

Note that each gate also has delays associated with each internal pathof the gate. For example, referring to FIG. 3C, the paths 331, 332 of anAND gate 330 have delays that can be analyzed using statistical timinganalysis. Notably, referring to FIG. 3D, a faster gate (i.e. internalpaths of that gate) has a smaller standard deviation (as shown by normaldistribution 340) and thus a smaller variation than a slower gate (asshown by normal distribution 341). Specifically, in this example, thefaster gate has only positive slack for an arc, which provides oneindication of more robustness than the slower gate (which might havenegative slack). Thus, using statistical timing analysis canadvantageously direct circuit optimization. In one embodiment,variations of input paths can affect the maximum operation (notincluding critical paths).

In static design, a designer has a budget allocated to handle delayvariations in the design. This budget (b) is typically a percentage (%)of a target clock. Unfortunately, the budget can only be set on theclock edges, which has the effect of tightening timing more thanrequired. Moreover, b changes over time because of optimization indownstream tools, refinement of models, and/or changes inspecifications, technology, or environment thereby, resulting indifferent timing constraint files. Therefore, static design has severaldisadvantages that result in sub-optimal designs and/or processes.

In contrast, in statistical design, the designer does not need todifferentiate between timing variability due to optimization indownstream tools, refinement of models, and/or changes inspecifications, technology, or environment. Specifically, in statisticaldesign, the static gate delay can be used as a mean (μ) and the budget bcan be used as a % standard deviation (σ) on the gate delay. Notably,statistical design does not suffer from over-constraining, therebyallowing each path to get its appropriate variation.

In one embodiment, the variability (or standard deviation) can bespecified by a user as percentage of the mean. For example, thevariability of each gate can be set to be the percentage of the clockperiod that is budgeted for delay variations. This sets the same numberfor all gates in the design. In an alternate embodiment, if delay rangesfor gates are known (and are different for different gates); an estimateof variability can be computed from the difference between the worstcase delay and the typical delay for each gate.

In summary, statistical timing analysis technology is developed in thecontext of handling process variations to guide the optimization forrobust circuits. Specifically, rather than rely on process data tospecify the delay model, the delay provided by static timing analysiscan be used as the mean and a user-specified percentage of the mean canbe used as the standard deviation. Thus, statistical timing analysisattributes the variation budget to the gates, while using the typicalbehavior for gate delays.

As a result, each path can be appropriately constrained. For example,longer paths have larger variation with bigger opportunity forstatistical cancellation to appear on the mean delay. Using statisticaltiming analysis can advantageously drive logic changes that favoroptimization metrics beneficial for robust circuits.

FIG. 4 illustrates an exemplary technique 400 for generating circuits ina design flow for an implementation process. Step 401 receives librarydata for a design including timing models. Step 402 defines a robustcircuit based on at least two of negative slack, endpoint slackdistribution, timing constraint violations, and total negative slack.Step 403 uses statistical timing analysis to drive logic changes thatgenerate improved robust circuits in the design.

The statistical timing analysis models a statistical delay distributionon an arc (i.e. a path between pins) of the design. Specifically,statistical timing analysis can use a static timing delay associatedwith the arc in static timing analysis as a mean (step 404) and aspecified percentage of the mean as the standard deviation (step 405).The specified percentage can be obtained from an estimate of a clockbudget for variations or an estimate of delay variations on a gate. Inone embodiment, step 403 further includes determining a slackdistribution at endpoints of the design for use as a cost metric indesign optimization (step 406). For example, the cost metric can includecomputing a probability of an endpoint failing to meet timingconstraints. The probability is computed from statistical timinganalysis (which provides a probability density function for the arrivaltime at an end-point). Notably, this probability can also be used toimprove the robustness of the design.

In another embodiment, the statistical slack of a pin (defined as thedifference between the statistical mean required time and thestatistical mean arrival time) can be used to judiciously select pins onwhich optimization is to be performed. Since statistical timing is ableto differentiate pins with more critical paths from pins with fewercritical paths, i.e. such pins will have a worse statistical slack butidentical static slack, the optimization is able to identify a good setof pins in the design which will reduce the number of violating pathseffectively.

Technique 400 can be advantageously used in various optimization stepsof the integrated circuit (IC) design flow (e.g. by way of example andnot limitation synthesis, placement, clock tree analysis, and routing).

Although illustrative embodiments of the invention have been describedin detail herein with reference to the accompanying figures, it is to beunderstood that the invention is not limited to those preciseembodiments. They are not intended to be exhaustive or to limit theinvention to the precise forms disclosed.

For example, technique 400 (FIG. 4) can be implemented in one or morecomputer programs (e.g. tool sets) that execute on a system including atleast one processor. Each computer program can be implemented in ahigh-level procedural or object-oriented programming language, inassembly language, or in machine language. Suitable processors include,but are not limited to, general and special purpose microprocessors, aswell as other types of micro-controllers. Generally, a processor willreceive instructions and data from a read-only memory (ROM) and/or arandom access memory (RAM). A computer can include one or more storagedevices for storing data files. Exemplary storage devices can includemagnetic disks, such as internal hard disks and removable disks,magneto-optical disks, and optical disks. Storage devices suitable fortangibly embodying computer program instructions and data can includevarious types of non-volatile memory, e.g. EPROM, EEPROM, and flashmemory devices, magnetic disks such as internal hard disks and removabledisks, magneto-optical disks, and CDROM disks.

Accordingly, it is intended that the scope of the invention be definedby the following Claims and their equivalents.

1. A method of generating circuits in a design flow for animplementation process, the method comprising: receiving library datafor a design including timing models; defining a robust circuit based onat least one of worst negative slack and total negative slack as well asat least one of endpoint slack distribution and number of timingconstraint violations; and using statistical timing analysis to drivelogic changes that generate improved robust circuits in the design,wherein the statistical timing analysis models a statistical delaydistribution on an arc of the design in static timing analysis, whereinthe statistical delay distribution on the arc includes: using a statictiming delay associated with the arc in statistical timing analysis as amean; and using a specified percentage of the mean as the standarddeviation, wherein the specified percentage is obtained from one of anestimate of a clock budget for variations and an estimate of delayvariations on a gate
 2. The method of claim 1 wherein the statisticaltiming analysis further includes determining a slack distribution atendpoints of the design for use as a cost metric in design optimization.3. The method of claim 2 wherein the cost metric includes computing aprobability of an endpoint failing to meet timing constraints.
 4. Themethod in claim 2 wherein a statistical slack is used to identifybottlenecks in the design on which to carry out optimization.
 5. Acomputer-readable medium embodying instructions that when executed by aprocessor would provide a tool set for generating circuits in a designflow for an implementation process, the tool set comprising: means forreceiving library data for a design including timing models; means fordefining a robust circuit based on at least one of worst negative slackand total negative slack as well as at least one of endpoint slackdistribution and number of timing constraint violations; and means forusing statistical timing analysis to drive logic changes that generateimproved robust circuits in the design, wherein the statistical timinganalysis models a statistical delay distribution on an arc of the designin static timing analysis wherein the statistical delay distribution onthe arc includes: using a static timing delay associated with the arc instatistical timing analysis as a mean; and using a specified percentageof the mean as the standard deviation, wherein the specified percentageis obtained from one of an estimate of the clock budget for variationsand from an estimate of delay variations on a gate.
 6. Thecomputer-readable medium of claim 5, wherein means for using thestatistical timing analysis further includes means for determining aslack distribution at endpoints of the design for use as a cost metricin design optimization.
 7. The computer-readable medium of claim 5,wherein the cost metric includes computing a probability of an endpointfailing to meet timing constraints.
 8. The computer-readable medium ofclaim 5, wherein a statistical slack is used to identify bottlenecks inthe design on which to carry out optimization.